module fifo_32d_192w_wrapper #(
    parameter                           DATA_WIDTH = 192 ,
    parameter                           ADDR_WIDTH = 5
)(
    input                               clk ,
    input                               rst ,
    input   [9:0]                       ram_2p_cfg_register,

    input   [DATA_WIDTH-1:0]            din ,
    input                               wr_en ,
    input                               rd_en ,
    output  [DATA_WIDTH-1:0]            dout ,

    output                              full ,
    output                              empty
) ;

    localparam ADDR_DEPTH = (1<<ADDR_WIDTH) ; //the width of address

    wire ram_we_n ;
    wire [ADDR_WIDTH-1:0] wr_addr ;
    wire [ADDR_WIDTH-1:0] rd_addr ;

    DW_fifoctl_s1_sf #(
        .depth(ADDR_DEPTH) ,
        .ae_level(2) ,
        .af_level(ADDR_DEPTH-2) ,
        .err_mode(0) ,
        .rst_mode(0)
    ) fifo_conctroller (
        .clk            (clk) ,
        .rst_n          (~rst) ,

        .push_req_n     (~wr_en) , // FIFO push request
        .pop_req_n      (~rd_en) , // FIFO pop request
        .diag_n         (1'b1) ,

        .we_n           (ram_we_n) ,
        .empty          (empty) ,
        .almost_empty   () ,
        .half_full      () ,
        .almost_full    () ,
        .full           (full) ,
        .error          () ,
        .wr_addr        (wr_addr) ,
        .rd_addr        (rd_addr)
    ) ;

    ram_2p_32d_192w_wrapper inst_ram_2p_32d_192w_wrapper (
        .clk                    (clk) ,
        .ram_2p_cfg_register    (ram_2p_cfg_register) ,//10'b00_111_11_0_0_1

        .wren_n                 (ram_we_n),
        .waddr                  (wr_addr),
        .wdata                  (din),
        .rden_n                 (~rd_en),
        .raddr                  (rd_addr),
        .rdata                  (dout)
    ) ;

endmodule
